In an EPROM (Electrically Programmable and Erasable ROM) type of semiconductor memory, the commonly used type of memory cell is constructed from a transistor having a double-gate structure comprised of a control gate and a floating gate. To write data into this type of memory cell, a high potential (write potential VPP) is applied to each of a word line connected to the control gate and a bit line connected to the drain. The source is fixed at ground potential.
As a result of the application of the high-potential, a high electric field is produced in the neighborhood of the drain in the channel region of the memory cell, generating channel hot electrons. The hot electrons are injected into the floating gate by the high potential applied to the control gate. The hot electrons injected into the floating gate cause an increase in the threshold of the memory cell seen by the control gate, thereby allowing data to be stored.
FIG. 1 illustrates a portion of an EPROM in which a plurality of memory cells, having such a structure as described above, are arranged in an array. In FIG. 1, M1 through M4 denote memory cells, WL1 and WL2 denote word lines, BL1 and BL2 denote bit lines, 1A and 1B denote column decoders, 2 through 5 denote decode signals from the column decoders, and 6 denotes a row decoder. D1, D2, H1, and H2 denote bit line select transistors, and S denotes a transistor for writing a data in a memory cell in responsive to a predetermined signal (write transistor).
In normal write mode and read mode, in order to select one of the bit lines, the bit line select transistors D1, D2, H1, H2 are selectively driven by decode signals 2-5 from the column decoders 1A and 1B.
Suppose now that the memory cell M1 is written into. Then, the bit line BL1 and the word line WL1 are selected with the result that they are supplied with the high potential. At this time, the other memory cell M2 having its drain connected to the selected bit line BL1 and its control gate maintained at ground potential is in a nonselected state, but its drain is supplied with the high potential. If the number of memory cells connected to one bit line is N, (N-1) cells are placed in such a state. When memory cells are in such a state, electrical stress is applied to their drains. In cases where the quality of their gate oxide layers is poor, the leakage of electrons injected into their floating gates may occur, and thus data that has be written into once may be erased.
Therefore, a reliability test is made to study data holding characteristics of drains of memory cells. This test is performed by applying a high potential to the bit lines and putting the word lines in the nonselected state after all the memory cells have been written into. In order to perform the test on all the memory cells, it is required to test 2.sup.n bit lines when the number of column address pins is n. If, in this case, the test were repeated for each of the bit lines, the overall test time would become extremely long. To reduce the test time, therefore, conventional EPROMs have been equipped with an internal test function. In a test mode using this internal test function, all the decode signals output from the column decoders 1A, 1B in FIG. 1 are set to a high ("H") level, and all the bit-line select transistors D1, D2, H1, H2 are simultaneously rendered conductive. Further, the drain and gate of a write transistor S is applied the high write potential VPP as in the case of the writing of data.
At this time, the gates of the memory cells M1, M2 connected to the bit line BL1 are both at ground potential, so that they are both nonconductive. The same potential is applied to the drains of the memory cells. Subsequently, a check is made for reliability. Such is also the case with other bit lines.
Consider now a case where, as shown in FIG. 2, there is a defect in the bit line BL2, for example, a defective leakage path 7 extending from the bit line to ground. In FIG. 2, memory cells are omitted for simplicity. Short-circuiting of the bit line and the drain of a memory cell to the substrate or the word line will be considered as one of the causes for the defective leakage path. EPROMs with such a leakage path are generally disposed of as defective units; however, a column redundancy circuit could make them completely operating units. That is, if fuses were programmed beforehand in such a way that, when such an address signal as to select the transistors D1 and H2 is input, a redundancy select transistor DR is selected in place of the transistors D1 and H2, the defective bit line BL2 could be replaced with a redundancy bit line BLR.
In performing the above-described stress test on such a defective EPROM, however, a leakage current path is formed which extends from the drain of the write transistor S supplied with the write potential VPP through the bit-line select transistors D1 and H2, the bit line BL2 and the defective leakage path 7 to ground. Then, the potential at a node 11', to which the source of the transistor S is connected, will go lower than the potential at the node 11 in FIG. 1 because of voltage drop across the transistors S and D1, and parasitic resistance associated with the line connecting the transistors. Further, the potential at the node 12 in FIG. 2, to which the source of the transistor D1 is connected, will go lower than the potential at the node 11'. At the time of stress test, it is necessary that a potential equal to that at node 11 be applied to all the bit lines.
In the case of FIG. 2, however, only a potential equal to that at node 12 is applied not only to the bit line BL2 associated with the defective leakage path 7 but also to the normal bit line BL1. This will not allow memory cells connected to the bit line BL1 to be subjected to a satisfactory stress test. In FIG. 2, only two bit lines are shown connected to the node 12 for the purpose of simplifying illustration, but actually eight or sixteen bit lines are connected to the node. Thus, when the potential at the node 11' goes lower than that at the node 11, the voltage applied to bit lines connected to the node 11' by transistors other than the transistor D1 will become insufficient in magnitude at the time of stress test. In other words, if there were at least one bit line having such a leakage path extending to ground as described above among all the bit lines supplied with the write potential VPP through the write transistor S, applied stress to all the bit lines would become insufficient in level. This might well allow some cells to pass the stress test in spite of poor reliability of their drain data holding characteristics.
It is possible to detect a defective bit line having a leakage path to ground potential by a test and replace it with a normal column by the use of a redundancy feature. However, even if there are defective cells that were allowed to pass the stress test in spite of their poor drain data holding property because the applied stress was insufficient, they remain undetected. For this reason, EPROMs having a leakage path to ground potential are regarded as defective though they can be saved by using the column redundancy feature.
Meanwhile, such problems as described above are also encountered in performing a burn-in test on DRAMs. In the burn-in test, a potential higher than a usual power supply voltage is applied to word lines. At this time, a high electric field is applied to the gate of each memory cell, so that a gate oxide layer with poor voltage-withstanding property suffers breakdown. The word line connected to which the memory cell has suffered a breakdown in the gate oxide layer is subsequently replaced with a redundancy word line. By the way, in performing the burn-in test, a high potential supplied through an external terminal is applied to all the word lines in parallel. If, however, a leakage current path extending from a certain word line to ground is present, applied stress to all the word lines becomes an insufficient level at the time of a burn-in test as is the case with the stress test described above. For this reason, some word lines may pass the burn-in test.
As described above, the problems with EPROMs are that, if at least one defective bit line is present which is associated with a leakage path extending to ground potential, applied stress applied to all the bit lines becomes insufficient in level, some memory cells may pass the stress test in spite of their poor reliability for drain data holding property, and they are regarded as defective though they can be remedied by the use of the redundancy function.
Likewise, the problems with DRAMs are that, if at least one defective word line is present which is associated with a leakage path extending to ground potential, applied stress applied to all the word lines becomes insufficient in level, some word lines may pass the burn-in test, and they are regarded as defective though they can be remedied by the use of the redundancy function.
A first object of the present invention is to provide a semiconductor memory in which, in a stress test for checking memory cells for their reliability for drain data holding property, even if a certain bit line is defective, a normal stress potential is applied to other normal bit lines or bit lines in blocks other than a block containing the defective bit line, thereby permitting a proper check to be made for reliability.
A second object of the present invention is to provide a semiconductor memory in which, in a burn-in test for checking voltage-withstanding property of gate oxide layers of memory cells, even if a certain word line is defective, a normal stress potential is applied to other normal word lines, thereby permitting a proper burn-in test to be made.